Metal-oxide-semiconductor field-effect transistors (MOSFETs) are used as high frequency switches which can alternate between an on-state and an off-state. This enables the control of high load power with minimal power dissipation. Although the MOSFET can switch at high speeds due to the absence of minority carrier transport, input capacitance limits its performance.
In conventional extended drain MOS (EDMOS) transistors, the input capacitance is relatively large due to the large gate area and the large overlap between gate and drain regions. Due to this type of configuration, the upper cutoff frequency is usually limited by the charging and discharging of the input capacitance. In addition to the gate-to-source capacitance (CGS), a significant gate-to-drain capacitance (CGD) is known to exist due to the overlap of the gate. If the input capacitance is relatively high, a relatively high gate current is needed to operate the EDMOS. As a result, the gate switching loss will be significant, especially at switching frequencies beyond 1 MHz.
Moreover, in conventional EDMOS on fully depleted silicon on insulator (FDSOI) structures, breakdown at gate stack/drift region is expected to ensue with continuous VB2 increase to modulate drift/drain electric field in a dual ground plane (DGP) device. VB2 refers to the biasing condition of a back-gate underneath the drift region/BOX. This is a highly N-doped implanted ground plane (GP), located in a N-well and connected to a hybrid pad, for example. At this point, the drift region virtually has more doping, and the potential at a gate stack edge will reach its maximum voltage.
Also, breakdown at the oxide occurs and BVdss collapses as the oxide can no longer sustain such a high voltage. BVdss is a breakdown voltage at which the reverse-biased body-drift diode breaks down and significant current starts to flow between the source and drain by the avalanche multiplication process, while the gate and source are shorted together. Currently, maximum BVdss achieved by EDMOS structures on FDSOI is about 11V, limited mainly by electric field at the boundary between gate stack and drift region.